memory circuit
英 [ˈmeməri ˈsɜːkɪt]
美 [ˈmeməri ˈsɜːrkɪt]
存储电路
双语例句
- Stimulation was shown to drive the activity in the temporal lobe and hippocampus, key components of the brain's memory circuit.
刺激可以驱使颞叶和海马回的活性，这些是脑部记忆回路的主要部分。 - Slice memory interface circuit
片式存储器接口电路 - When the yellow power input lead is connected, power will always be supplied to the memory circuit even when the ignition key is turned off.
当连接黄色电源线时，即使点火钥匙关闭，也总是向记忆电路供电。 - An adiabatic static CMOS memory circuit to have ability in information recovery by means of analyzing equivalent circuit, choosing parameter and realizing complete function of sequential circuit is presented.
通过等效电路分析、考虑参数选取和整体时序电路的实现，提出具有信息恢复能力的静态绝热CMOS记忆电路。 - For solving this problem, the paper introduces a ultimate and design method to build share memory circuit with the using of general IC through a real project appliance.
通过一个具体的工程应用，介绍了使用普通集成电路构建共享存储器电路的基本原理和设计方法。 - The hardware system includes power supply circuit, clock reset circuit, JTAG model building circuit, decoding circuit, memory interface circuit, man-machine interface circuit and numeric control constant-current source interface circuit.
硬件系统主要包括电源电路、时钟复位电路、JTAG仿真接口电路，译码电路、存储器接口电路、人机接口电路、ADC转换电路和数控恒流源接口等。 - However, since memory circuit is very large and dense and the growing of its size is amazing, it is unpractical to extract the logic parameter directly with simulation tools.
然而，由于存储器单元密集和电路庞大的特点，并且存储器的增大极为迅速，使得用仿真工具直接提取逻辑参数并不现实，存储器的简化迫在眉睫。 - In this paper a synthesis for low power circuits is studied and an adiabatic ratioless dynamic memory circuit is expressed quantitatively in accordance with the theory of three essential circuit elements.
该文从电路三要素理论出发研究低功耗电路，定量描述绝热无比型动态记忆电路。 - The design of the system has its own separate watchdog and EEPROM memory circuit, therefore it can improve system reliability.
系统设计有独立的看门狗电路和EEPROM存储器电路，提高了系统可靠性。 - Design for Share Memory Circuit with Multiple Port
多端口共享存贮器电路设计 - The principle diagram of personal computer and single chip processor share random access memory circuit and a method of program access is given.
本文绘出了PC系列微机与单片机共享RAM电路的原理图和程序访问的方法。 - A threshold memory circuit for realizing arbitrary multivalued sequential logic
一种用于实现任意基数值时序逻辑的阈值存储电路 - The system is mainly consisted of the modules such as the 8-route digital signal generator, data sample and memory circuit, control circuit, the wave restore and display circuit.
其主要模块有任意可设定8路数字信号发生器、数据采集存储电路、控制电路、波形还原显示电路。 - As Memory circuit densities increase, the extraction time of logic parameter is beginning unendurable.
随着Memory的集成度越来越高，逻辑参数的提取时间变得无法忍受。 - Analyzed memory interface circuit, JTAG debug interface circuit and LCD display interface circuit on core board.
分析了核心板的存储器接口电路、JTAG调试接口电路和LCD显示接口电路。 - The Implementation of Personal Computer and Single Chip Processor Share Random Access Memory Circuit
PC系列微机与单片机共享RAM电路的实现 - The hardware module of the monitoring system includes the clock circuit, power supply circuit, the reset circuit, the memory extended circuit, the data acquisition circuit, the serial interface circuit, simulation interface.
监测系统的硬件采用模块化设计，监测系统的硬件模块包括：时钟电路、电源电路、复位电路、存储器设计、数据采集电路、串行通信和仿真接口。 - Secondly, design and simulation of FPGA-based random logic and embedded memory BIST circuit were completed based on pseudo random testing theory and March C algorithm, and characteristic analysis was used to realize the compression and analysis of testing response signal.
其次，结合伪随机测试原理及MarchC算法完成了基于FPGA的随机逻辑和嵌入式存储器的内建自测试电路设计和仿真，并采用特征分析法实现对测试响应信号的压缩和分析。 - The circuit diagrams and the principle analysis of power circuit, crystal circuit, reset circuit, memory circuit and other input/ output interface circuits are given in this thesis.
论文给出了主解码部分的电源、晶振、复位电路、存储器、其他输入输出接口等关键模块的电路原理图和原理分析。 - Thesis research on the design of passive UHF RFID tag chip front-end analog circuitry and EEPROM memory circuit system structure transformation.
论文主要研究放在无源UHFRFID电子标签芯片前端模拟电路的设计和EEPROM存储器电路的系统结构改造。 - Meanwhile, it designs the communication circuit and memory circuit.
介绍了通信电路和存储电路。 - Next, the paper designs a memory control timing circuit. This circuit can control the memory circuit from reader issuing commands and data to completing flash memory or a read operation.
之后，论文设计了一种存储器控制时序电路，该电路可以完成在读卡器发出指令及数据之后到对存储器擦、写或读操作完成之前对存储器电路的控制。 - The hardware circuit includes CCD signal acquisition circuit, CPLD and PIC microcontrollers, signal processing circuits, high-speed A/ D converter sampling circuit, DMA circuit, memory circuit and digital signal transmission circuit.
系统的硬件电路包括CCD信号采集电路、CPLD和PIC单片机电路、信号调理电路、高速A/D采样转换电路、DMA电路、存储电路、数字信号传输电路等。 - The design of the system mainly includes the clock circuit design, peripheral memory circuit design, gigabit Ethernet interface design, image sampling input/ output interface design, and so on.
该系统的设计主要包括时钟电路设计、外围存储器电路设计、千兆以太网接口设计、图像采集输入输出接口设计等等。 - Designed around the expansion of the circuit, such as the power module circuit, memory module circuit, video capture module circuit and the IIC module circuit.
设计了周围的扩展电路，如电源模块电路、存储器模块电路、视频采集模块电路和ⅡC模块电路等。 - The hardware circuit includes the aspects like collecting circuit, extended memory circuit, CPLD internal logic circuit, power supply and reset circuit.
系统的硬件电路包括图像采集电路、存储器扩展电路、CPLD内部逻辑电路、电源和复位电路等功能模块。 - By the charging circuit, protection circuits, data acquisition circuit, a balanced circuit, display circuit, memory circuit, communication circuit, the alarm circuit.
由充电电路、保护电路、采集电路、均衡电路、显示电路、存储电路、通讯电路、报警电路组成。 - The design flow and methodology of IP Block is discussed and a memory interface circuit ( SGRAM Interface) is designed in chapter 4.
第四章讨论IPBlock的设计流程和方法，并具体设计了一个存储器接口电路（SGRAM接口）。 - By diagnosing memory circuit with four cells, 100% fault coverage is achieved corresponding to bridge fault, open fault and coupling fault.
以四单元存储器为诊断实例，针对桥接故障、开路故障以及耦合故障，实现了100%故障覆盖率。